Registration

Opening Remarks: Erik Volkerink, Verigy (General Chair)
 
Keynote address: Future of ATE? Jim Healy, Sony

Session1 : ATE Software: Beyond Vectors, timing and levels

1.1: Automated Test Program Generation for Automotive Devices, Peter Huber, J.
       Vollmar - Teradyne inc., A Drappa - Robert Bosch GmbH

1.2: The Unified Platform Architecture: A software framework for Rapid Test
       program development on Multiple ATE, Radford Nguyen, Pete
       Hodakievic, Advanced Micro Devices - USA
   
1.3: Connecting ATE to EDA through STDF V4-2007-enabling fast and
       robust scan fail data collection for EDA diagnosis, Geir Eide, Huaxing
       Tang, Wu Yang, Mentor Graphics Corp. - USA, Michael Braun, Markus
       Seuring, Verigy Germany GmbH

Panel: New Frontiers in ATE Software, Moderator: Debora Ahlgren

        Al Crouch, ASSET InterTech, Inc. - USA
        Ric Dokken, RogueVation, Inc. - USA
        Dan Glotter, Optimal Test - USA
        Peter Hodavievic, Advanced Micro Devices - USA
        Chris Lemoine, LTX Credence - USA

Lunch and Networking game

Sponsor Table Tour

Session 2: Enabling Protocol Aware Testing: Are we there yet?

2.1: Protocol-Aware ATE with native Memory emulation mode: Enabling a
       paradigm shift for testing complex SoC, Alex Roskin, Daniel Blank,
       Verigy Germany GmbH, Shawn Molavi, Broadcom Corp - USA

2.2: De-Embedding Errors in Protocol-Aware EVM test using Vector Signal
       Analysis, Devin Morris, Roos Instruments Inc. USA
  
2.3: Protocol-Aware RF test future for Mobile communications, Gregory
       Smith, Teradyne Inc. - USA

Session 3: Test Equipment for More than Moore
   
3.1: Looking into the Future of ATE Load boards, Phil Warwick, R&D
       Circuits, Inc. - USA
   
3.2: CMOS Image test future industry challenges, Larry Levy, FormFactor,
        Inc. - USA
  
3.3: The Energy Footprint of ATE & It’s Effect on CoT, Carl Kasinski, LTX
       Credence - USA

Invited speaker: Herb Reiter, 3D IC Test Eco-System

Session 4: Tackling the Testing 3rd Dimension : The Next Paradigm in Semiconductor Test
   
4.1: Pre-bond Probing of TSVs in 3D Stacked ICs, Brandon Noia,
       Krishnendu Chakrabarty, Duke University - USA
   
4.2: 3D TSV Test from an ATE Perspective: Myths, Challenges, and
       Solutions, Ben Rogel-Favila, Jay Orbon, Dhruva Acharyya, Robert
       Smith, Markus Seuring, Scott Chesnut, Matt Losey, Duncan Gurley,
       Erik Volkerink, Verigy US Inc.
   
4.3: KGD Probing of TSVs at 40µm Array Pitch, Ken Smith, Peter Hanaway,
       Mike Jolley, Reed Gleason, Chris Fournier, Eric Strid Cascade Micro Tech
       
Closing Panel: TSV Quality imperative: Closer Supply-chain collaboration for
highest quality TSV stacks, Moderator: - Ron Leckie

        Bill Bottoms  3MTS - USA
        Lonny Block   Micron Technology, Inc. - USA
        Gary Fleeman   Advantest America Corp. - USA
        Joe Foerstel   Altera Corp. - USA
        Mike Slessor   MicroProbe, Inc. - USA
 
Closing Remarks and iPad2 Raffle